/* 
	implementation of memory manager and cache miss handler 
	nothing is put into function sections so that all is included into the driver
	Cache Notes:
		only single cache lines are supported since the code generator does only support natural loads
		multiple cachelines would collide with LRU and cannot be implemented for all cases
		automatic DMA prefetching is enabled
			prefetched cachelines not currently present and not in async write back progress
		atomic write back is performed in 2 stages to make use of latencies between misses, the 2nd stage is toggled 
			in the asm epilogue
		simple asynchronous write back transfer is performed (faster) for areas specified by the program
			(calls to SPUAddCacheWriteRangeAsync), no DMA sync is performed
		to not let atomic write backs, prefetches or async transfers transfer old memory, the back transfer addresses 
			are always compared against the new cache line address (the last 4 and the present one),
			prefetches are nullified if equal, async transfers are syncd and atomic transfers are just copying the merged present contents

*/ 
#include "StdAfx.h"
































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































